Current Research Focus

Ning Guo et al., 2016.

Analog and Hybrid Computing on Silicon Chips

Analog and hybrid computers were widely used in the 1940s and 1950s for simulating physical and other systems, obeyed by differential equations; such computers were even instrumental in NASA's programs. They were large and difficult to make and operate. Starting in the 1960s and 1970s, they were displaced by digital computers thanks to advances in digital MOS (Metal-Oxide-Semiconductor) semiconductor technology, which made it possible to place large numbers of digital switches on a single silicon chip. At the time, this technology was not suitable for high-performance analog circuits, and analog computers were abandoned. Today, however, analog MOS circuit design and fabrication is a highly advanced art. Thus, in our group we asked the question: What would analog and hybrid computers look like, and what could they do, if they were integrated on a silicon chip? Our research answered this question. Our chips obtain approximate solutions of nonlinear differential equations faster than a digital computer, and with smaller computational energy. In some cases, the approximate solution can then be fed to a digital computer as an excellent first guess, for refinement. We believe that analog and hybrid computers on silicon chips can complement digital computers. Our present analog/hybrid computer chip can solve up to 16 coupled differential equations in about 1 millisecond, with about 0.1 microjoules per problem order. Two such chips have been combined on a board, for a 32nd-order system that interfaces with a digital computer through a USB port. This gives us the best of both worlds: analog for approximate computations, achieved with low energy and high speed; and digital for algorithmic programming, storage, and computation with high precision.

IEEE Spectrum article on analog computing

Selected publications:

N. Guo, Y. Huang, T. Mai, S. Patil, C. Cao, M. Seok, S. Sethumadhavan, and Y. Tsividis, "Energy-Efficient Hybrid Analog/Digital Approximate Computation in Continuous Time", IEEE Journal of Solid-State Circuits, vol. 51, no. 7, pp. 1514-1524, July 2016.

Y. Huang, N. Guo, M. Seok, Y. Tsividis, and S. Sethumadhavan, “Hybrid Analog-Digital Solution of Nonlinear Partial Differential Equations”, Proceedings, 50th Annual IEEE/ACM International Symposium on Microarchitecture, October 14-18, 2017.

Y. Huang, N. Guo, M. Seok, Y. Tsividis, and S. Sethumadhavan, “Evaluation of an analog accelerator for linear algebra”, Proceedings, 43d ACM/IEEE International Symposium on Computer Architecture (ISCA), pp. 570-582, Seoul, June 2016.

G. Cowan, R. Melville, and Y. Tsividis, “A VLSI analog computer / digital computer accelerator”, IEEE Journal of Solid-State Circuits, vol. 41, no. 1, pp. 42-53, January 2006.

Yu Chen et al., 2017.

Event-Driven, Continuous-Time Digital Circuits, Signal Processing and Data Acquisition

Years ago, we became convinced that the fixed-frequency clock used in conventional computers in a sense wastes the time dimension: the time interval taken by one clock period remains the same, and thus carries no information. In signal processing, the uniform sampling used to produce such signals from analog ones is suboptimal, as it results in fixed time resolution, whether the signal varies fast or slowly. We decided to allow the zeros and ones inherent in a digital representation to switch at any appropriate instant of time, resulting in signals in which the individual bits, rather than being sequences, are functions of continuous time. We process these signals using asynchronous circuits. However, the time details in such signals are an integral part of signal representation; this makes them different from signals encountered in asynchronous digital computing, which are sequences of digital values, with the time between successive values not playing an essential role. Our approach provides an opportunity to take advantage of the time dimension, unlike the case with clocked and conventional asynchronous systems. We have produced silicon chips for both data acquisition and digital signal processing, all in continuous time, and with power dissipation that automatically decreases as the signal activity decreases. These systems have better spectral properties than conventional digital systems.

Selected publications:

Y. Chen, X. Zhang, Y. Lian, R. Manohar, and Y. Tsividis, “A Continuous-Time Digital IIR Filter with Signal-Derived Timing and Fully Agile Power Consumption”, accepted for publication, IEEE Journal of Solid-State Circuits.

S. Patil, A. Ratiu, D Morche, and Y. Tsividis, “A 3–10 fJ/conv-step Error-Shaping Alias-Free Continuous-Time ADC”, IEEE Journal of Solid-State Circuits, vol. 51, no. 4, pp. 908-918, April 2016.

C. Vezyrtzis, W. Jiang, S. Nowick, and Y. Tsividis, “A flexible, event-driven digital filter with frequency response independent of input sample rate”, IEEE Journal of Solid-State Circuits, vol. 49, no. 10, pp. 2292-2304, October 2014.

M. Kurchuk, C. Weltin-Wu, D. Morche, and Y. Tsividis, “Event-Driven GHz-Range Continuous-Time Digital Signal Processor with Activity-Dependent Power Dissipation”, IEEE Journal of Solid-State Circuits, vol. 47, no. 9, pp. 2164-2173, September 2012.

Y. Tsividis, "Event-driven data acquisition and digital signal processing – A tutorial", IEEE Transactions on Circuits and Systems II, Jump-start tutorial, vol. 57, no. 8, pp. 577-581, August 2010.

B. Schell and Y. Tsividis, “A continuous-time ADC/DSP/DAC system with no clock and activity-dependent power dissipation”, IEEE Journal of Solid-State Circuits, vol. 43, no. 11, pp. 2472-2481, November 2008.

Y. Tsividis, “Continuous-time digital signal processing”, Electronics Letters, vol. 39, no. 21, pp. 1551-1552, 16 October 2003.